Combinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams Sherief Reda Ashraf Salem Computer & Systems Eng. 6,086,626 (the “'626 Patent”) disclose a filtering based methods for combinational equivalence checking. This report presents a technique for improving the performance of the existing Dept. of Electrical Engineering Indian Institute of Technology Bombay viren@ee.iitb.ac.in EE 709: Testing & Verification of VLSI Circuits Lecture – 10 (Jan 24, 2012) Combinational equivalence checking (CEC) plays an important role in EDA. BDD is used for one partition and SAT is used for the other partition. Abstract: The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. No. Combinational equivalence checking is one of the key components in today’s hardware veriﬁcation methodology. We argue that SAT is a more robust and ﬂexi-ble engine of Boolean reasoning for the CEC application than BDDs, which have traditionally been the method of choice. In this work we address the problem of combinational equivalence checking for threshold circuits. No. Combinational Equivalence Checking Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab. rithms to the combinational equivalence checking (CEC) problem. Structuralsimilarity of the two designs are exploited by existing BDD, SAT, or ATPG based methods. We propose a new algorithm, to obtain compact functional representation of threshold elements. Preliminary results on a simple framework for SAT based CEC show a speedup of up to two orders of mag- Its immediate application is verifying functional equivalence of combinational circuits after multi-level logic synthesis [6]. In Combinational Equivalence Checking Using Satisﬁability and Recursive Learning João Marques-Silva Thomas Glass Instituto Superior Técnico Siemens AG Cadence European Labs/INESC Corporate Technology 1000 Lisboa, Portugal 81730 Munich, Germany e-mail: jpms@inesc.pt e-mail: thomas.glass@mchp.siemens.de We give the proof of correctness, and analyze its runtime complexity. U.S. Pat. Dept. 6,026,222 (the “'222 Patent”) discloses a combinational equivalence checking method based on a partition of the circuits. This problem arises in a number of computer-aided design (CAD) applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). 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